Embodiments of the invention relates to an array substrate of a thin film transistor liquid crystal display (TFT-LCD) and a method of manufacturing the same.
Recently, TFT-LCDs have prevailed in flat panel display market due to the characteristics of excellent display quality, relatively low manufacturing cost, low power consumption, and low radiation, and even the display quality is still gradually improved with the development of technology.
A TFT-LCD has a configuration formed by assembling an array substrate and a color filter substrate. An array substrate of a TFT-LCD typically adopts bottom gate TFTs of back channel etching type as switch devices. As shown in FIGS. 1 and 1a, the array substrate comprises a plurality of gate lines 1, a plurality of data lines 5 perpendicular to the gate lines 1, and pixel regions defined by intersecting of the adjacent gate lines and data lines. Each pixel comprises a TFT as a switch device, a pixel electrode 10, and a common electrode line 11. The TFT comprises a gate electrode 2, a gate insulating layer 4, a semiconductor layer 3, a source electrode 6 and a drain electrode 7, and an ohmic contact 13, which are covered by a passivation layer 8. A via hole 9 is formed over the drain electrode 7 in the passivation layer. The pixel electrode 10 is connected with the drain electrode 7 of the TFT through the via hole 9 in the passivation layer 8. A storage capacitor is formed between the pixel electrode 10 and the gate line 1 together with the common electrode line 11. Light-blocking strips are formed on both sides of the pixel electrode 10 parallel to the data line 5 to reduce light leakage from the pixel after the array substrate and the color filter substrate are assembled together.
A 5-Mask (photolithography) process is conventionally employed to manufacture an array substrate of a TFT-LCD, which comprises the following five steps as shown in FIG. 2.
Step 201 of forming a gate electrode and a gate line on a base substrate by depositing and patterning a gate metal film;
Step 202 of forming a gate insulating layer, a semiconductor layer and an ohmic contact on the substrate after step 201 by depositing and patterning a metal film;
Step 203 of forming a source electrode and a drain electrode and a data line on the substrate after step 202 by depositing and patterning a source-drain metal film;
Step 204 of forming a passivation layer on the substrate after step 203 and forming a via hole therein by patterning; and
Step 205 of forming a pixel electrode on the substrate after step 204 by depositing and patterning a pixel conductive layer.
The above-mentioned process is a typical 5-Mask process, each step of which comprises depositing a film, forming a photoresist pattern by coating, exposing, and developing a photoresist layer on the film, etching the film with the photoresist mask, and so on.
In the above method and the array substrate thus manufactured, since a storage capacitor is formed between the pixel electrode 10 and the gate line 1 together with the common electrode line 11, as shown in FIG. 1b, a two layer structure including the gate insulating layer 4 and the passivation layer 8 is formed between the pixel electrode 10 and the gate line 1 (not shown in FIG. 1b) together with the common electrode line 11 so that the distance between the pixel electrode 10 and the gate line 1 and the distance between the pixel electrode 10 and the common electrode 11 become relatively large. Therefore, the storage capacitance become relatively small, and the switching voltage become relatively high, which adversely affects the display quality of the finished display device. In addition, since exposure process is performed five times in the 5-Mask process, the manufacturing period is relatively long, reducing productivity and increasing manufacturing cost.